Version Differences for VHDLでいこう!

(VHDLシミュレーター)
(VHDLの例文)
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  == VHDLの例文 ==    == VHDLの例文 == 
  <pre>    <pre> 
- library IEEE;   + library IEEE; --ライブラリー宣言  
  use IEEE.std_logic_1164.all;    use IEEE.std_logic_1164.all; 
  use IEEE.numeric_std.all;    use IEEE.numeric_std.all; 
- entity counter is   + entity counter is --エンタティーの宣言  
  port(    port( 
  clk:in std_logic;    clk:in std_logic; 
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  end entity counter    end entity counter 
- Architecture arc_counter of counter is   + Architecture arc_counter of counter is --アーキテクチャーの宣言  
  signal qq:unsigned(4 downto 0);    signal qq:unsigned(4 downto 0); 
  begin    begin 
    + process(clk,rst) --プロセス文  
    + begin  
  if rst=0 then     if rst=0 then  
  Qout<="0000";    Qout<="0000"; 
Line 54:
  qq<=qq+1;    qq<=qq+1; 
  end if;    end if; 
    + end process;  
  Qout<=(std_logic_vector)qq;    Qout<=(std_logic_vector)qq; 
  end Architecture;    end Architecture;