Version Differences for VHDLでいこう!

(VHDLシミュレーター)
(VHDLの例文)
Line 48:
  begin    begin 
  if rst=0 then     if rst=0 then  
- Qout="0000";   + Qout<="0000";  
- qq="0000";   + qq<="0000";  
  else if clk'event and clk=1 then    else if clk'event and clk=1 then 
- Qout=(std_logic_vector)(qq+1);   + qq<=qq+1;  
  end if;    end if; 
    + Qout<=(std_logic_vector)qq;  
  end Architecture;    end Architecture;